A conventional memory module may include both memory devices and one or more data buffers and may operate at a double data rate (DDR). If the data rate of data input into the data buffer is different from that of the data output from the data buffer, the frequency of an operating clock for the data buffer may be different from the frequency of an operating clock for the memory devices during a normal mode of operation. Typically, during a normal mode operation, the frequency of the operating clock for the data buffer is at least twice the frequency of the operating clock for the memory devices.
Accordingly, in order to test the memory devices in a test mode of operation, a tester may need to operate using the frequency of the operating clock for the data buffer, thus, a high speed tester is typically used. However, the use of a high speed tester may increase test costs and, therefore, increasing the manufacturing costs of a memory module.
Referring now to FIG. 1, a block diagram illustrating a conventional memory module will be discussed. In a conventional memory module the frequency of a buffer clock signal CK_BUFFER, which is an operating clock for a data buffer 15, may be twice the frequency of a memory clock signal CK_MEMORY, which is an operating clock for first and second memory devices 11 and 13 during a normal mode of operation.
As illustrated in FIG. 1, the conventional memory module 100 includes first and second Dynamic Random Access Memories (DRAMs) 11 and 13 and a data buffer 15. The first and second DRAMs 11 and 13 input and/or output data in response to a memory clock signal CK_MEMORY. The data buffer 15 buffers write data input using an input/output pin DQ, and outputs the write data to the first and second DRAMs 11 and 13 in response to a buffer clock signal CK_BUFFER during a normal mode of operation. The data buffer 15 also buffers read data output from the first and second DRAMs 11 and 13 and outputs the read data to the input/output pin DQ in response to a buffer clock CK_BUFFER during a normal mode of operation. The data buffer 15 includes first through fourth registers (151-154), first through fourth delay units (155-158), and a multiplexer 159.
During a write operation, the first register 151 samples the write data input through the input/output pin DQ in response to a rising edge of the buffer clock CK_BUFFER, and the second register 152 samples the write data input through the input/output pin DQ in response to a falling edge of the buffer clock CK_BUFFER. As shown in FIG. 2, a timing diagram illustrating write operations of the memory module of FIG. 1, write data DI0 and DI2 is output REG0_Q from the first register 151, and the write data DI1 and DI3 is output REG1_Q from the second register 152.
Output REG0_Q of the first register 151 is delayed 1½ cycles of the buffer clock CK_BUFFER by a first delay unit 155, and delayed data MIO0_Q is input into the first DRAM 11 at a rising and/or falling edge of the memory clock signal CK_MEMORY. Similarly, output REG1_Q of the second register 152 is delayed 1 cycle of the buffer clock CK_BUFFER by a second delay unit 156, and delayed data MIO1_Q is input into the second DRAM 13 at a rising and/or falling edge of the memory clock signal CK_MEMORY.
Now referring to FIG. 3, a timing diagram of a read operation of the memory module of FIG. 1 will be discussed. During a read operation, read data MIO0_Q, i.e., DO0 and DO2, is output from the first DRAM 11 at a rising and/or falling edge of the memory clock signal CK_MEMORY, and read data MIO1_Q, i.e., DO1 and DO3, is output from the second DRAM 13. Read data DO0 and DO2 is delayed ½ a cycle of the buffer clock CK_BUFFER by a third delay unit 157, and read data DO1 and DO3 is delayed 1 cycle of the buffer clock CK_BUFFER by a fourth delay unit 158.
Output REG2_D of the third delay unit 157 is sampled as output REG2_Q at a rising edge of the buffer clock CK_BUFFER by the third register 153, and output REG3_D is sampled as output REG3_Q at a falling edge of the buffer clock CK_BUFFER by the fourth register 154. The multiplexer 159 selects output REG2_Q at a rising edge of the buffer clock CK_BUFFER or output REG3_Q at a falling edge of the buffer clock CK_BUFFER and outputs REG2_Q or REG3_Q to the input/output pin DQ.
As described above, in order to test conventional memory modules, for example, the memory module of FIG. 1, the tester typically operates using the frequency of the buffer clock CK_BUFFER. However, the frequency of the buffer clock CK_BUFFER is typically at least twice the frequency of the memory clock signal CK_MEMORY, thus, a high-speed tester is typically used. The use of a high speed tester for a conventional memory module may increase test costs and, therefore, increasing the manufacturing costs of a memory module.